The present invention relates generally to computer processors. More specifically, the present invention relates to power savings with an array structure of processor cells.
A processing cell contains logic elements for executing an operation on data according to an instruction. Increasingly, larger numbers of processing cells are connected together in one processor to accomplish a greater number of more complex processing tasks. For instance, a processor having cells that are arranged in an array of M rows and N columns is capable of processing M×N operations during each clock cycle. Further, each cell in the array can be individually programmed to perform a unique operation, such that the processor could accomplish M×N different operations during a single clock cycle.
In digital systems, dynamic power consumption dominates a system's overall power consumption. Each cell consumes dynamic power in two ways: when its input is changing, and when its internal registers are clocked. Some processing applications require only a portion of the number of cells in a processor to execute a particular function. However, a cell that is not being used for a certain application will still consume dynamic power by having its registers continually clocked while it awaits to be enabled.
Some uses for processors, such as in a handheld computing device or wireless communication device for example, benefit from reduced power consumption. Reduced power consumption allows for a smaller power supply, and thus a more efficient design of such devices. Also, a device with reduced processor power consumption can achieve a longer battery life. Accordingly, there exists a need for a method and arrangement for saving power in a processor.